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authorJan Beulich <jbeulich@suse.com>2019-11-08 09:06:24 +0100
committerJan Beulich <jbeulich@suse.com>2019-11-08 09:06:24 +0100
commitf74a6307279f162e892e570448dc2433963db1d8 (patch)
tree8511668a57eb3a30335ab74559d0adc94bdec513 /gas
parentx86: convert RegSIMD and RegMMX from bitfield to enumerator (diff)
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x86: convert RegMask and RegBND from bitfield to enumerator
This is to further shrink the operand type representation.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-i386.c13
2 files changed, 13 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1ff0c2598b7..75e056c7ab0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
2019-11-08 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (optimize_encoding, build_modrm_byte,
+ check_VecOperations, parse_real_register): Use "class" instead
+ of "regmask" and "regbnd" fields.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
* config/tc-i386.c (match_mem_size, operand_size_match,
operand_type_register_match, pi, check_VecOperands, match_template,
check_byte_reg, check_long_reg, check_qword_reg, process_operands,
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 20cd1adf85b..ba6b82af189 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4154,7 +4154,7 @@ optimize_encoding (void)
else
return;
}
- else if (i.tm.operand_types[0].bitfield.regmask)
+ else if (i.tm.operand_types[0].bitfield.class == RegMask)
{
i.tm.base_opcode &= 0xff;
i.tm.opcode_modifier.vexw = VEXW0;
@@ -7682,8 +7682,8 @@ build_modrm_byte (void)
for (op = 0; op < i.operands; op++)
{
if (i.types[op].bitfield.class == Reg
- || i.types[op].bitfield.regbnd
- || i.types[op].bitfield.regmask
+ || i.types[op].bitfield.class == RegBND
+ || i.types[op].bitfield.class == RegMask
|| i.types[op].bitfield.class == SReg
|| i.types[op].bitfield.class == RegCR
|| i.types[op].bitfield.class == RegDR
@@ -9238,7 +9238,7 @@ check_VecOperations (char *op_string, char *op_end)
else if ((mask = parse_register (op_string, &end_op)) != NULL)
{
/* k0 can't be used for write mask. */
- if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
+ if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
{
as_bad (_("`%s%s' can't be used for write mask"),
register_prefix, mask->reg_name);
@@ -10935,7 +10935,8 @@ parse_real_register (char *reg_string, char **end_op)
if (!cpu_arch_flags.bitfield.cpuavx512f)
{
- if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
+ if (r->reg_type.bitfield.zmmword
+ || r->reg_type.bitfield.class == RegMask)
return (const reg_entry *) NULL;
if (!cpu_arch_flags.bitfield.cpuavx)
@@ -10948,7 +10949,7 @@ parse_real_register (char *reg_string, char **end_op)
}
}
- if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
+ if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
return (const reg_entry *) NULL;
/* Don't allow fake index register unless allow_index_reg isn't 0. */