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| author |   blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 20:55:31 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 20:55:31 +0000 |
| commit | 4911012d267519d104a3123783c9b86bddc59f39 (patch) | |
| tree | c32a907b146c5d031a6fb9bc6b4c73f3c69b7d7c /target-ppc | |
| parent | Enable 64bit mode on interrupts (diff) | |
| download | qemu-kvm-4911012d267519d104a3123783c9b86bddc59f39.tar.gz qemu-kvm-4911012d267519d104a3123783c9b86bddc59f39.tar.bz2 qemu-kvm-4911012d267519d104a3123783c9b86bddc59f39.zip | |
Implement mtfsf.L encoding
Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 09b3945ee..386343ede 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2420,9 +2420,10 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) } /* mtfsf */ -GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) +GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT) { TCGv_i32 t0; + int L = ctx->opcode & 0x02000000; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); @@ -2431,7 +2432,10 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_reset_fpstatus(); - t0 = tcg_const_i32(FM(ctx->opcode)); + if (L) + t0 = tcg_const_i32(0xff); + else + t0 = tcg_const_i32(FM(ctx->opcode)); gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) != 0)) { |