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authorAurelien Jarno <aurelien@aurel32.net>2010-02-01 19:58:46 +0100
committerAurelien Jarno <aurelien@aurel32.net>2010-04-09 18:21:51 +0200
commit36a013c956bec033f6261070671b569c95976194 (patch)
tree3de87197fedf250991774a2439094d8d24bd95d7
parentsh7750: handle MMUCR TI bit (diff)
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target-sh4: MMU: fix mem_idx computation
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0 corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to user mode (SR_MD = 0). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 33b8f5546cc16eaa3d89fe133a9843c794b65d6c)
-rw-r--r--target-sh4/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 895b978d3..7f9527a83 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1905,7 +1905,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
ctx.bstate = BS_NONE;
ctx.sr = env->sr;
ctx.fpscr = env->fpscr;
- ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
+ ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */